ST STM32G4 Series Reference Manual page 983

RM0440
26.5.48 HRTIM timer x fault register (HRTIM_FLTxR) (x = A to F)
Address offset: Block A: 0x0E8
Address offset: Block B: 0x168
Address offset: Block C: 0x1E8
Address offset: Block D: 0x268
Address offset: Block E: 0x2E8
Address offset: Block F: 0x368
Reset value: 0x0000 0000
31 30 29
FLT
Res. Res. Res.
LCK
rwo
15 14 13
Res. Res. Res. Res.
Bit 31 FLTLCK: Fault sources lock
0: FLT1EN..FLT6EN bits are read/write
1: FLT1EN..FLT6EN bits are read only
The FLTLCK bit is write-once. Once it has been set, it cannot be modified till the next system reset.
Bits 30:6 Reserved, must be kept at reset value.
Bit 5 FLT6EN: Fault 6 enable
0: Fault 6 input ignored
1: Fault 6 input is active and disables HRTIM outputs
Bit 4 FLT5EN: Fault 5 enable
0: Fault 5 input ignored
1: Fault 5 input is active and disables HRTIM outputs
Bit 3 FLT4EN: Fault 4 enable
0: Fault 4 input ignored
1: Fault 4 input is active and disables HRTIM outputs
Bit 2 FLT3EN: Fault 3 enable
0: Fault 3 input ignored
1: Fault 3 input is active and disables HRTIM outputs
Bit 1 FLT2EN: Fault 2 enable
0: Fault 2 input ignored
1: Fault 2 input is active and disables HRTIM outputs
Bit 0 FLT1EN: Fault 1 enable
0: Fault 1 input ignored
1: Fault 1 input is active and disables HRTIM outputs
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
FLT6
Res. Res. Res.
RM0440 Rev 1
High-resolution timer (HRTIM)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
FLT5 FLT4 FLT3
EN EN EN EN
rw rw rw rw
17 16
Res. Res.
1 0
FLT2 FLT1
EN EN
rw rw
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