Flash Status Register (Flash_Sr) - ST STM32G4 Series Reference Manual

Embedded Flash memory (FLASH) for category 2 devices
4.7.5

Flash status register (FLASH_SR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
OPTV RD
Res. Res.
ERR ERR
rc_w1 rc_w1
Bits 31:17 Reserved, must be kept at reset value.
Bits 13:10 Reserved, must be kept at reset value.
174/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
FAST
Res. Res.
ERR
rc_w1
Bit 16 BSY: Busy
This indicates that a Flash operation is in progress. This is set on the beginning
of a Flash operation and reset when the operation finishes or when an error
occurs.
Bit 15 OPTVERR: Option validity error
Set by hardware when the options read may not be the one configured by the
user. If option haven't been properly loaded, OPTVERR is set again after each
system reset.
Cleared by writing 1.
Bit 14 RDERR: PCROP read error
Set by hardware when an address to be read through the D-bus belongs to a
read protected area of the flash (PCROP protection). An interrupt is generated if
RDERRIE is set in FLASH_CR.
Cleared by writing 1.
Bit 9 FASTERR: Fast programming error
Set by hardware when a fast programming sequence (activated by FSTPG) is
interrupted due to an error (alignment, size, write protection or data miss). The
corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at
the same time.
Cleared by writing 1.
Bit 8 MISERR: Fast programming data miss error
In Fast programming mode, 32 double words must be sent to flash successively,
and the new data must be sent to the flash logic control before the current data is
fully programmed. MISSERR is set by hardware when the new data is not
present in time.
Cleared by writing 1.
Bit 7 PGSERR: Programming sequence error
Set by hardware when a write access to the Flash memory is performed by the
code while PG or FSTPG have not been set previously. Set also by hardware
when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set
due to a previous programming error.
Cleared by writing 1.
24 23 22
Res. Res. Res. Res.
8 7 6
MISS PGS SIZ PGA
ERR ERR ERR ERR
rc_w1 rc_w1 rc_w1 rc_w1
RM0440 Rev 1
21 20 19 18
Res. Res. Res.
5 4 3 2
WRP PROG
Res.
ERR
ERR
rc_w1 rc_w1
RM0440
17 16
Res. BSY
r
1 0
OP
EOP
ERR
rc_w1 rc_w1