ST STM32G4 Series Reference Manual page 718

Digital-to-analog converter (DAC)
21.7.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28
rw rw rw
15 14 13 12
rw rw rw
Bits 31:20 DACC1DHRB[11:0]: DAC channel1 12-bit left-aligned data B
These bits are written by software. They specify 12-bit data for DAC channel1 when the DAC
operates in Double data mode.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software.
They specify 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
21.7.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
DACC1DHRB[7:0]
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 DACC1DHRB[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software. They specify 8-bit data for DAC channel1 when the DAC
operates in Double data mode.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software. They specify 8-bit data for DAC channel1.
21.7.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2)
This register is available only on dual-channel DACs. Refer to
implementation.
718/2083
27 26 25
DACC1DHRB[11:0]
rw rw rw rw
11 10 9
DACC1DHR[11:0]
rw rw rw rw
27 26 25
Res. Res. Res.
11 10 9
rw rw rw rw
24 23 22
rw rw rw
8 7 6
rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res.
rw rw
5 4 3 2
Res. Res.
rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
DACC1DHR[7:0]
rw rw rw rw
Section 21.3: DAC
RM0440
17 16
Res. Res.
1 0
Res. Res.
17 16
Res. Res.
1 0
rw rw