Table 255. Dma Request - ST STM32G4 Series Reference Manual

RM0440
1. Configure the corresponding DMA channel as follows:
–
–
–
–
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4. Enable TIMx.
5. Enable the DMA channel.
This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let's
take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.
Note: A null value can be written to the reserved registers.
27.3.33 TIM1/TIM8/TIM20 DMA requests
The TIM1/TIM8/TIM20 can generate a DMA request, as shown in
DMA acronym
TIM_UP
TIM_CH1
TIM_CH2
TIM_CH3
TIM_CH4
TIM_COM
TIM_TRIG
27.3.34 Debug mode
When the microcontroller enters debug mode (Cortex
counter can either continue to work normally or stop, depending on DBG_TIMx_STOP
configuration bit in DBG module.
The behavior in debug mode can be programmed with a dedicated configuration bit per
timer in the Debug support (DBG) module.
For safety purposes, when the counter is stopped, the outputs are disabled (as if the MOE
bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have
their control taken over by the GPIO controller (OSSI bit = 0), typically to force a Hi-Z.
DMA channel peripheral address is the DMAR register address.
DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
Number of data to transfer = 3 (see note below).
Circular mode disabled.
Advanced-control timers (TIM1/TIM8/TIM20)

Table 255. DMA request

DMA request
Update
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Commutation (COM)
Trigger
RM0440 Rev 1
Table 255.
Enable control bit
UDE
CC1DE
CC2DE
CC3DE
CC4DE
COMDE
TDE
®
-M4 with FPU core halted), the TIMx
1129/2083
1181