ST STM32G4 Series Reference Manual page 471

RM0440
Bits 7:2 Reserved
Bit 1 X1FULL: X1 buffer full flag. The buffer is flagged as full if the number of available spaces is
less than the FULL_WM threshold. The number of available spaces is the difference between
the write pointer and the least recent sample currently in use.
This flag is set and cleared by hardware, or by a reset.
Note: after the last available space in the X1 buffer is filled there is a delay of 3 clock cycles
Bit 0 YEMPTY: Y buffer empty flag. The buffer is flagged as empty if the number of unread data is
less than the EMPTY_WM threshold. The number of unread data is the difference between
the read pointer and the current output destination address.
This flag is set and cleared by hardware, or by a reset.
Note: after the last sample is read from the Y buffer there is a delay of 3 clock cycles before
17.4.7 FMAC Write Data register (FMAC_WDATA)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Bits 31:16 Reserved
Bits 15:0 WDATA: Write data.
17.4.8 FMAC Read Data register (FMAC_RDATA)
Address offset: 0x1C
Reset value: 0x0000 0000
0: X1 buffer not full. If the WIEN bit is set, the interrupt request will be asserted until the flag
is set. If DMAWEN is set, DMA write channel requests will be generated until the flag is set.
1: X1 buffer full.
before the X1FULL flag goes high. To avoid any risk of overflow it is recommended to
insert a software delay after writing to the X1 buffer before reading the FMAC_SR.
Alternatively, a FULL_WM threshold of 2 can be used.
0: Y buffer not empty. If the RIEN bit is set, the interrupt request will be asserted until the
flag is set. If DMAREN is set, DMA read channel requests will be generated until the flag is
set.
1: Y buffer empty.
the YEMPTY flag goes high. To avoid any risk of underflow it is recommended to insert
a software delay after reading from the Y buffer before reading the FMAC_SR.
Alternatively, an EMPTY_WM threshold of 2 can be used.
28 27 26 25
Res. Res. Res.
12 11 10 9
When a write access to this register occurs, the write data are transferred to the address
offset indicated by the WRITE pointer. The pointer address is automatically incremented
after each write access.
24 23 22
Res. Res. Res. Res.
8 7 6
WDATA[15:0]
w
RM0440 Rev 1
Filter Math Accelerator (FMAC)
21 20 19 18
Res. Res. Res.
5 4 3 2
17 16
Res. Res.
1 0
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