ST STM32G4 Series Reference Manual page 926

High-resolution timer (HRTIM)
26.5.11 HRTIM master timer compare 4 register (HRTIM_MCMP4R)
Address offset: 0x02C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MCMP4[15:0]: Master timer compare 4 value
This register holds the master timer compare 4 value. It is either the preload register or the active
register if preload is disabled.
The compare value must be above or equal to 3 periods of the f
CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
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28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
MCMP4[15:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
clock, that is 0x60 if
RTIM
H
RM0440
17 16
Res. Res.
1 0
rw rw