RM0440
22.3.2
VREFBUF calibration control register (VREFBUF_CCR)
Address offset: 0x04
Reset value: 0x0000 00XX
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:6 Reserved, must be kept at reset value.
Bits 5:0 TRIM[5:0]: Trimming code
22.3.3
VREFBUF register map
The following table gives the VREFBUF register map and the reset values.
Offset Register name
VREFBUF_CSR
0x00
Reset value
VREFBUF_CCR
0x04
Reset value
Refer to
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
These bits are automatically initialized after reset with the trimming value stored in the Flash
memory during the production test. Writing into these bits allows to tune the internal
reference buffer voltage.
Table 187. VREFBUF register map and reset values
Section 2.2 on page 78
Voltage reference buffer (VREFBUF)
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
for the register boundary addresses.
RM0440 Rev 1
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
TRIM[5:0]
rw
rw
rw
rw
17
16
Res.
Res.
1
0
rw
rw
0
0 0
1 0
TRIM[5:0]
x
x
x
x
x
x
735/2083
735
Need help?
Do you have a question about the STM32G4 Series and is the answer not in the manual?
Questions and answers