Figure 385. Edge-Aligned Pwm Waveforms (Arr=8) - ST STM32G4 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
mode on page
In the following example, we consider PWM mode 1. The reference PWM signal tim_ocxref
is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then tim_ocxref is held at
'1. If the compare value is 0 then tim_ocxref is held at '0.
aligned PWM waveforms in an example where TIMx_ARR=8.
Counter register
CCRx=4
CCRx=8
CCRx>8
CCRx=0
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to
mode on page
In PWM mode 1, the reference signal tim_ocxref is low as long as TIMx_CNT>TIMx_CCRx
else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload
value in TIMx_ARR, then tim_ocxref is held at 100%. PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
'00 (all the remaining configurations having the same effect on the tim_ocxref/tim_ocx
signals). The compare flag is set when the counter counts up, when it counts down or both
when it counts up and down depending on the CMS bits configuration. The direction bit
1214/2083
1191.

Figure 385. Edge-aligned PWM waveforms (ARR=8)

0
tim_ocxref
CCxIF
tim_ocxref
CCxIF
'1'
tim_ocxref
CCxIF
'0'
tim_ocxref
CCxIF
1195.
RM0440 Rev 1
1 2 3 4
Figure 385 shows some edge-
5 6 7 8
Downcounting
RM0440
Upcounting
0 1
MSv62327V1