ST STM32G4 Series Reference Manual page 460

Filter Math Accelerator (FMAC)
Table 106. Valid combinations for read and write methods (continued)
WIEN
0
1
The filter is started by writing to the FMAC_PARAM register with the following bit-field
values:
–
–
–
–
–
If less than N + d -
remains low. If the WIEN bit is set in the FMAC_CR register, then the interrupt request will
be asserted immediately to request the processor to write
the buffer, via the FMAC_WDATA register. It will remain asserted until the X1FULL flag goes
high in the FMAC_SR register. The interrupt service routine should check the X1FULL flag
after every
flag goes high. Similarly, if the DMAWEN bit is set in the FMAC_CR register, DMA write
channel requests will be generated until the X1FULL flag goes high.
The filter will calculate the first output sample when at least N samples have been written
into the X1 buffer (including any pre-loaded samples).
EMPTY_WM
When
2
the FMAC_SR register will go low. If the RIEN bit is set in the FMAC_CR register, the
interrupt request will be asserted to request the processor to read
the buffer, via the FMAC_RDATA register. It will remain asserted until the YEMPTY flag
goes high. The interrupt service routine should check the YEMPTY flag after every
EMPTY_WM
2
high. If the DMAREN bit is set in the FMAC_CR, DMA read channel requests will be
generated until the YEMPTY flag goes high.
The filter will continue to operate in this fashion until it is stopped by the software resetting
the START bit.
17.3.9 Implementing IIR filters with the FMAC
The FMAC supports IIR filters of length N, where N is the number of feed-forward taps or
coefficients. The number of feedback coefficients, M, can be any value from 1 to N-1. Only
direct form 1 implementations can be realised, so filters designed for other forms need to be
converted.
The minimum memory requirement for an IIR filter with N feed-forward coefficients and M
feed-back coefficients is 2N + 2M:
–
–
–
If M = N-1, then the maximum filter length that can be implemented is N = 64.
460/2083
RIEN
1
0
FUNC = 8 (FIR filter);
P = N (number of coefficients);
Q = "Don't care";
R = Gain;
START = 1;
FULL_WM
values have been pre-loaded in the X1 buffer, the X1FULL flag
2
FULL_WM
writes to the FMAC_WDATA register, and repeat the transfer until the
2
output samples have been written into the Y buffer, the YEMPTY flag in
reads from the FMAC_RDATA register, and repeat the transfer until the flag goes
N + M coefficients
N input samples
M output samples
DMAWEN DMAREN
1 0
0 1
RM0440 Rev 1
Write
DMA Interrupt
Interrupt DMA
FULL_WM
additional samples into
2
EMPTY_WM
samples from
2
RM0440
Read