ST STM32G4 Series Reference Manual page 730

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32G4 Series:

Table of Contents

Digital-to-analog converter (DAC)

DAC sawtooth mode register (DAC_STMODR)

Address offset: 0x60

Reset value: 0x0000 0000

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 STINCTRIGSEL2[3:0]: DAC channel2 sawtooth increment trigger selection

Refer to the trigger selection tables for the details on trigger configuration and mapping.

The mapping is the same as for TSEL2[3:0] except that the software trigger is replaced by

Software trigger B.

Note: These bits are available only on dual-channel DACs. Refer to

Bits 19:16 STRSTTRIGSEL2[3:0]: DAC channel2 sawtooth reset trigger selection

Refer to the trigger selection tables for the details on trigger configuration and mapping.

The mapping is the same as for TSEL2[3:0].

Note: These bits are available only on dual-channel DACs. Refer to

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:8 STINCTRIGSEL1[3:0]: DAC channel1 sawtooth increment trigger selection

Refer to the trigger selection tables for the details on trigger configuration and mapping.

The mapping is the same as for TSEL1[3:0] except that the software trigger is replaced by

Software trigger B

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:0 STRSTTRIGSEL1[3:0]: DAC channel1 sawtooth reset trigger selection

Please refer to the trigger table (Each DAC instance has different mapping)

Mapping is same as TSEL1[3:0]

STINCTRIGSEL2[3:0]

STINCTRIGSEL1[3:0]

implementation.

RM0440 Rev 1

STRSTTRIGSEL2[3:0]

STRSTTRIGSEL1[3:0]

Section 21.3: DAC

Chapters

Table of Contents

Do you have a question about the STM32G4 Series and is the answer not in the manual?