Figure 284. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow) - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus
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Advanced-control timers (TIM1/TIM8/TIM20)

Figure 284. Counter timing diagram, update event with ARPE=1 (counter underflow)

Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Auto-reload active
1060/2083
tim_psc_ck
CEN
tim_cnt_ck
06
(UIF)
FD
register
Write a new value in TIMx_ARR
register
05
04
03
02
01
FD
RM0440 Rev 1
00
01
02
03
04
05
36
36
RM0440
06
07
MSv62314V1

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