Bit Banding; Table 3. Stm32G4 Series Memory Map And Peripheral Register Boundary - ST STM32G4 Series Reference Manual

RM0440

Table 3. STM32G4 Series memory map and peripheral register boundary

Bus Boundary address
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF 1 KB
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF 1 KB
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
APB1
0x4000 2000 - 0x4000 23FF
Cont.
0x4000 1C00 - 0x4000 1FFF 1 KB
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF 1 KB
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
1. Refer to Table 1: STM32G4 Series memory
GPIO ports and peripherals available on your device. the memory area corresponding to unavailable GPIO ports or
peripherals are reserved (highlighted in gray).
2.3

Bit banding

The Cortex
each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a
word in the alias region has the same effect as a read-modify-write operation on the
targeted bit in the bit-band region.
In the STM32G4 Series devices both the peripheral registers and the SRAM are mapped to
a bit-band region, so that single bit-band write and read operations are allowed. The
operations are only available for Cortex
masters (e.g. DMA).
addresses
Size
(bytes)
1 KB Reserved
SPI3/I2S3
1 KB SPI2/I2S2
1 KB Reserved
1 KB IWDG
WWDG
RTC & BKP
1 KB
Registers
1 KB TAMP
1 KB CRS
Reserved
1 KB Reserved
1 KB TIM7
1 KB TIM6
TIM5
1 KB TIM4
1 KB TIM3
1 KB TIM2
density, Table 2: Product specific features
®
-M4 with FPU memory map includes two bit-band regions. These regions map
RM0440 Rev 1
(1)
(continued)
Peripheral
Section 38.9.10: SPI/I2S register map
Section 38.9.10: SPI/I2S register map
Section 41.4.6: IWDG register map
Section 42.4.4: WWDG register map
Section 34.6.21: RTC register map
Section 35.6.9: TAMP register map
Section 7.6.5: CRS register map
Section 28.5.31: TIMx register
mapSection 30.4.9: TIMx register map
Section 30.4.9: TIMx register map
Section 28.5.31: TIMx register map
Section 28.5.31: TIMx register map
Section 28.5.31: TIMx register map
Section 28.5.31: TIMx register map
®
-M4 with FPU accesses, and not from other bus
Peripheral register map
-
-
-
-
and to the device datasheets for the
83/2083
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