Table 378. Smbus With Pec Configuration - ST STM32G4 Series Reference Manual

RM0440
Master Tx/Rx NBYTES + PEC+ STOP
Master Tx/Rx NBYTES + PEC + ReSTART
Timeout detection
The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the
I2C_TIMEOUTR register. The timers must be programmed in such a way that they detect a
timeout before the maximum time given in the SMBus specification.
•
t
TIMEOUT
In order to enable the t
programmed with the timer reload value in order to check the t
TIDLE bit must be configured to '0' in order to detect the SCL low level timeout.
Then the timer is enabled by setting the TIMOUTEN in the I2C_TIMEOUTR register.
If SCL is tied low for a time greater than (TIMEOUTA+1) x 2048 x t
flag is set in the I2C_ISR register.
Refer to
(max t
Caution: Changing the TIMEOUTA[11:0] bits and TIDLE bit configuration is not allowed when the
TIMEOUTEN bit is set.
•
t
LOW:SEXT
Depending on if the peripheral is configured as a master or as a slave, The 12-bit
TIMEOUTB timer must be configured in order to check t
t
LOW:MEXT
the same value for the both.
Then the timer is enabled by setting the TEXTEN bit in the I2C_TIMEOUTR register.
If the SMBus peripheral performs a cumulative SCL stretch for a time greater than
(TIMEOUTB+1) x 2048 x t
detection on page 1854
Refer to
Caution: Changing the TIMEOUTB configuration is not allowed when the TEXTEN bit is set.
Bus Idle detection
In order to enable the t
with the timer reload value in order to obtain the t
configured to '1 in order to detect both SCL and SDA high level timeout.
Then the timer is enabled by setting the TIMOUTEN bit in the I2C_TIMEOUTR register.
If both the SCL and SDA lines remain high for a time greater than (TIMEOUTA+1) x 4 x
t
, the TIMEOUT flag is set in the I2C_ISR register.
I2CCLK
Refer to
t = 50 µs)
IDLE

Table 378. SMBUS with PEC configuration

Mode
Slave Tx/Rx with PEC
check
TIMEOUT
Table 379: Examples of TIMEOUTA settings for various I2CCLK frequencies
= 25 ms).
TIMEOUT
and t check
LOW:MEXT
for a master. As the standard specifies only a maximum, the user can choose
section, the TIMEOUT flag is set in the I2C_ISR register.
Table 380: Examples of TIMEOUTB settings for various I2CCLK frequencies
check, the 12-bit TIMEOUTA[11:0] field must be programmed
IDLE
Table 381: Examples of TIMEOUTA settings for various I2CCLK frequencies (max
Inter-integrated circuit (I2C) interface
SBC bit RELOAD bit AUTOEND bit PECBYTE bit
x
x
1
check, the 12-bit TIMEOUTA[11:0] bits must be
, and in the timeout interval described in
I2CCLK
IDLE
RM0440 Rev 1
0 1
0 0
0 x
TIMEOUT
I2CCLK
for a slave and
LOW:SEXT
parameter. The TIDLE bit must be
1
1
1
parameter. The
, the TIMEOUT
Bus idle
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