Table 41. Rcc Register Map And Reset Values - ST STM32G4 Series Reference Manual

RM0440
6.4.30 Peripherals independent clock configuration register (RCC_CCIPR2)
Address: 0x9C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:20 QSPISEL[1:0]: QUADSPI clock source selection
Set and reset by software.
Bits 19:2 Reserved, must be kept at reset value.
Bits 1:0 I2C4SEL[1:0]: I2C4 clock source selection
These bits are set and cleared by software to select the I2C4 clock source.
6.4.31 RCC register map
The following table gives the RCC register map and the reset values.
Offset Register
RCC_CR
0x00
Reset value
RCC_ICSCR
0x04
Reset value
RCC_CFGR
0x08
Reset value
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
00: system clock selected as QUADSPI kernel clock
01: HSI16 clock selected as QUADSPI kernel clock
10: PLL "Q" clock selected as QUADSPI kernel clock
11: reserved
00: PCLK selected as I2C4 clock
01: System clock (SYSCLK) selected as I2C4 clock
10: HSI16 clock selected as I2C4 clock
11: reserved

Table 41. RCC register map and reset values

0 0 0 0 0 0
HSITRIM[6:0]
1 0 0 0 0 0 0 X X X X X X X X
MCOPRE MCOSEL
[2:0] [3:0]
0 0 0 0 0 0 0
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
0 0 0 0
HSICAL[7:0]
RM0440 Rev 1
Reset and clock control (RCC)
21 20 19 18
QSPISEL
Res. Res.
[1:0]
rw rw
5 4 3 2
Res. Res. Res. Res.
0 0 0
PPRE2 PPRE1
HPRE[3:0]
[2:0] [2:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 16
Res. Res.
1 0
I2C4SEL[1:0]
rw rw
SWS SW
[1:0] [1:0]
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