ST STM32G4 Series Reference Manual page 31

RM0440
29.8.6
29.8.7
29.8.8
29.8.9
29.8.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . 1386
29.8.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . 1387
29.8.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . 1387
29.8.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . 1388
29.8.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . 1389
29.8.15 TIMx option register 1 (TIMx_OR1)(x = 16 to 17) . . . . . . . . . . . . . . . 1392
29.8.16 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . . . . 1392
29.8.17 TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . . . . . . 1393
29.8.18 TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . . . . 1393
29.8.19 TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . . . . 1396
29.8.20 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . 1396
29.8.21 TIM16/TIM17 DMA address for full transfer
29.8.22 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398
30 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
30.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
30.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
30.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
30.3.1
30.3.2
30.3.3
30.3.4
30.3.5
30.3.6
30.3.7
30.3.8
30.3.9
30.3.10 TIM6/TIM7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
30.4 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
30.4.1
30.4.2
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . 1383
TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 1386
(TIMx_DMAR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
TIM6/TIM7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
TIM6/TIM7 internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
TIM6/TIM7 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
TIM6/TIM7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
TIM6/TIM7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1412
TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1414
RM0440 Rev 1
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