Figure 191. Triggered-Half Mode Example - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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have a master-slave system.The slave converter synchronization is continuously adjusted

based on the previous switching period of the master converter.

This is done using the capture unit. The switching period of the master converter is

captured, divided by 2 and then stored in the compare 2 register by hardware. The compare

2 register contains a value equal to half of the captured period, which is the master

converter switching period. The compare 2 event can then be used to trigger a second

timing unit that manages the slave converter.

This mode is enabled by setting the TRGHLF bit in the HRTIM_TIMxCR2 register. This bit

cannot be changed once the timer is operating (TxEN bit set).

The triggered-half mode must not be used simultaneously with other modes using CMP2

(dual channel dac trigger, interleaved and balanced idle modes).

The initial value CMP2 can be written by the user, but is ignored once the first capture is

triggered. The preload mechanism is disabled for CMP2 when the TRGHLF bit is reset.

(HRTIM_CHA1)

(HRTIM_CHB1)

(HRTIM_CHA2)

Figure 191. Triggered-half mode example

Set on EEV1 (EEV1 triggers Capture1)

Reset on EEV2

EEV1 Blanking on TIMA_CMP1 (avoid frequency run-away)

Set on CMP2 (triggered-half) or EEV1 blanking by TIMA_TA2

(TB1 is set if EEV1 occurs between CMP1 and CMP2, else on CMP2)

Reset on EEV3

Set on TA_CMP1

Reset on TA_CMP2

RM0440 Rev 1

High-resolution timer (HRTIM)

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