ST STM32G4 Series Reference Manual page 1000

High-resolution timer (HRTIM)
26.5.60 HRTIM burst mode trigger register (HRTIM_BMTRGR)
Address offset: 0x3A4
Reset value: 0x0000 0000
31 30 29
OCHP TDEEV
EEV8 EEV7
EV
rw rw rw
15 14 13
TBCMP TBCMP
TCRST TBREP TBRST
2 1
rw rw rw
Bit 31 OCHPEV: On-chip event
A rising edge on the hrtim_bm_trg input (connected to general purpose timer TRGO output) triggers
a burst mode entry (see
Bit 30 EEV8: External event 8 (TIMD filters applied)
The external event 8 conditioned by TIMD filters is starting the burst mode operation.
Bit 29 EEV7: External event 7 (TIMA filters applied)
The external event 7 conditioned by TIMA filters is starting the burst mode operation.
Bit 28 TDEEV8: Timer D period following external event 8
The timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst
mode operation.
Bit 27 TAEEV7: Timer A period following external event 7
The timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst
mode operation.
Bit 26 TECMP2: Timer E compare 2 event
Refer to TACMP1 description.
Bit 25 TECMP1: Timer E compare 1 event
Refer to TACMP1 description.
Bit 24 TEREP: Timer E repetition
Refer to TAREP description.
Bit 23 TFCMP1: Timer F compare 1 event
Refer to TACMP1 description.
Bit 22 TDCMP2: Timer D compare 2 event
Refer to TACMP1 description.
Bit 21 TFREP: Timer F repetition
Refer to TAREP description.
Bit 20 TDREP: Timer D repetition
Refer to TAREP description.
Bit 19 TDRST: Timer D reset or roll-over
Refer to TARST description.
Bit 18 TFRST: Timer F reset
Refer to TARST description.
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28 27 26 25
TAEEV TECMP TECMP
8 7 2 1
rw rw rw rw
12 11 10 9
TACMP TACMP
2 1
rw rw rw rw
Table 200
24 23 22
TF TDCM
TEREP
CMP1 P2
rw rw rw
8 7 6
MSTC MSTC
TAREP TARST
MP4
rw rw rw
for details).
RM0440 Rev 1
21 20 19 18
TF TF
TDREP TDRST
REP RST
rw rw rw rw
5 4 3 2
MSTC MSTC MSTRE
MP3 MP2 MP1 P
rw rw rw rw
RM0440
17 16
TCCM
TCREP
P1
rw rw
1 0
MSTRS
SW
T
rw rw