Figure 607. Sai Functional Block Diagram - ST STM32G4 Series Reference Manual

RM0440
39.3 SAI functional description
39.3.1 SAI block diagram
Figure 607
external signals.
SAI
SAI_ACR1
sai_a_
Clock generator
ker_ck
Audio block A
sai_pclk
sai_b_
Clock generator
ker_ck
Audio block B
SAI_BCR1
The SAI is mainly composed of two audio subblocks with their own clock generator. Each
audio block integrates a 32-bit shift register controlled by their own functional state machine.
Data are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by
DMA in order to leave the CPU free during the communication. Each audio block is
independent. They can be synchronous with each other.
An I/O line controller manages a set of 4 dedicated pins (SD, SCK, FS, MCLK) for a given
audio block in the SAI. Some of these pins can be shared if the two subblocks are declared
as synchronous to leave some free to be used as general purpose I/Os. The MCLK pin can
be output, or not, depending on the application, the decoder requirement and whether the
audio block is configured as the master.
If one SAI is configured to operate synchronously with another one, even more I/Os can be
freed (except for pins SD_x).
The functional state machine can be configured to address a wide range of audio protocols.
Some registers are present to set-up the desired protocols (audio frame waveform
generator).
shows the SAI block diagram while

Figure 607. SAI functional block diagram

sai_a_gbl_it sai_a_dma
FIFO
Configuration
and status
registers
FIFO
Configuration
and status
registers
sai_b_gbl_it sai_b_dma
RM0440 Rev 1
Table 356
32-bit APB bus
APB Interface
Audio block A
FIFO ctrl
FSM
32-bit shift register
Audio block B
FIFO ctrl
FSM
32-bit shift register
APB Interface
32-bit APB bus
Serial audio interface (SAI)
and Table 357 list SAI internal and
FS_A
SCK_A
SD_A
MCLK_A
FS_B
SCK_B
SD_B
MCLK_B
D[4:1]
PDM_IF
CK[4:1]
MSv45358V3
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