ST STM32G4 Series Reference Manual page 582

Analog-to-digital converters (ADC)
20.4.13 Single conversion mode (CONT=0)
In Single conversion mode, the ADC performs once all the conversions of the channels.
This mode is started with the CONT bit at 0 by either:
•
Setting the ADSTART bit in the ADC_CR register (for a regular channel)
•
Setting the JADSTART bit in the ADC_CR register (for an injected channel)
•
External hardware trigger event (for a regular or injected channel)
Inside the regular sequence, after each conversion is complete:
•
The converted data are stored into the 16-bit ADC_DR register
•
The EOC (end of regular conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
Inside the injected sequence, after each conversion is complete:
• The converted data are stored into one of the four 16-bit ADC_JDRy registers
•
The JEOC (end of injected conversion) flag is set
•
An interrupt is generated if the JEOCIE bit is set
After the regular sequence is complete:
•
The EOS (end of regular sequence) flag is set
•
An interrupt is generated if the EOSIE bit is set
After the injected sequence is complete:
• The JEOS (end of injected sequence) flag is set
•
An interrupt is generated if the JEOSIE bit is set
Then the ADC stops until a new external regular or injected trigger occurs or until bit
ADSTART or JADSTART is set again.
Note: To convert a single channel, program a sequence with a length of 1.
20.4.14 Continuous conversion mode (CONT=1)
This mode applies to regular channels only.
In continuous conversion mode, when a software or hardware regular trigger event occurs,
the ADC performs once all the regular conversions of the channels and then automatically
restarts and continuously converts each conversions of the sequence. This mode is started
with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the
ADC_CR register.
Inside the regular sequence, after each conversion is complete:
•
The converted data are stored into the 16-bit ADC_DR register
•
The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
•
The EOS (end of sequence) flag is set
•
An interrupt is generated if the EOSIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
582/3748 RM0440 Rev 1
RM0440