ST STM32G4 Series Reference Manual page 984

High-resolution timer (HRTIM)
26.5.49 HRTIM timer x control register 2 (HRTIM_TIMxCR2) (x = A to F)
Address offset: Block A: 0x0EC
Address offset: Block B: 0x16C
Address offset: Block C: 0x1EC
Address offset: Block D: 0x26C
Address offset: Block E: 0x2EC
Address offset: Block F: 0x36C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
FEROM[1:0] BMROM[1:0]
rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bit 20 TRGHLF: Triggered-half mode
This bitfield defines whether the compare 2 register is behaving in standard mode (compare match
issued as soon as counter equal compare), or in triggered-half mode (see
mode).
0: CMP2 register is written by the user only (standard compare mode)
1: CMP2 value is set by hardware as soon as a capture 1 event occurs. It is loaded with the
(capture 1 divided by 2) value. The initial value can be written by the user (as long as TRGHLF is
reset), but is ignored once the first capture has been triggered (the preload mechanism is
disabled for CMP2 when the TRGHLF bit is set).
Note: This bitfield must not be modified once the counter is enabled (TxCEN bit set).
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 GTCMP3: Greater than compare 3 PWM mode
This bit defines the compare 3 operating mode.
0: The compare 3 event is generated when the counter is equal to the compare value (compare
match mode)
1: The compare 3 event is generated when the counter is greater than the compare value. If the
compare value is changed on-the-fly, the new compare value is compared with the current counter
value and an output SET or RESET can be generated.
Bit 16 GTCMP1: Greater than compare 1 PWM mode
This bit defines the compare 1 operating mode.
0: The compare 1 event is generated when the counter is equal to the compare value (compare
match mode)
1: The compare 1 event is generated when the counter is greater than the compare value. If the
compare value is changed on-the-fly, the new compare value is compared with the current counter
value and an output SET or RESET can be generated.
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28 27 26 25
Res. Res. Res.
12 11 10 9
ADROM[1:0] OUTROM[1:0]
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
ROM[1:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
TRG
Res. Res. Res.
HLF
rw
5 4 3 2
Res. UDM Res. DCDR
rw rw
Section : Triggered-half
RM0440
17 16
GT GT
CMP3 CMP1
rw rw
1 0
DCDS DCDE
rw rw