Figure 263. 3-Phase Interleaved Buck Converter Control - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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The master timer is responsible for the phase management: it defines the phase

relationship between the converters by resetting the timers periodically. The phase-shift is

360° divided by the number of phases, 120° in the given example.

The duty cycle is then programmed into each of the timers. The outputs are defined as

The ADC trigger can be generated on TxCMP2 compare event. Since all ADC trigger

sources are phase-shifted because of the converter topology, it is possible to have all of

them combined into a single ADC trigger to save ADC resources (for instance 1 ADC

regular channel for the full multi-phase converter).

counter CMP1

Transition mode power factor correction

The basic operating principle is to build up current into an inductor during a fixed Ton time.

This current then decays during the Toff time, and the period is re-started when it becomes

null. This is detected using a Zero Crossing Detection circuitry (ZCD), as shown on

264. With a constant Ton time, the peak current value in the inductor is proportional

to the rectified AC input voltage, which provides the power factor correction.

HRTIM_CHA1 set on master timer period, reset on TACMP1

HRTIM_CHB1 set on master timer MCMP1, reset on TBCMP1

HRTIM_CHC1 set on master timer MCMP2, reset on TCCMP1

Figure 263. 3-phase interleaved buck converter control

RM0440 Rev 1

High-resolution timer (HRTIM)

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