ST STM32G4 Series Reference Manual page 276

Reset and clock control (RCC)
6.4.21 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR)
Address offset: 0x6C
Access: no wait state, word, half-word and byte access
31 30 29 28
Res. Res. Res. Res. Res.
15 14 13 12
ADC345 ADC12
Res. Res. Res.
SMEN SMEN
rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 RNGEN: RNG enable
Set and cleared by software.
0: RNG disabled
1: RNG enabled
Bit 25 Reserved, must be kept at reset value.
Bit 24 AESMEN: AESM clocks enable
Set and cleared by software.
0: AESM clocks disabled
1: AESM clocks enabled
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 DAC4SMEN: DAC4 clock enable
Set and cleared by software.
0: DAC4 clock disabled
1: DAC4 clock enabled during sleep and stop modes
Bit 18 DAC3SMEN: DAC3 clock enable
Set and cleared by software.
0: DAC3 clock disabled
1: DAC3 clock enabled during sleep and stop modes
Bit 17 DAC2SMEN: DAC2 clock enable
Set and cleared by software.
0: DAC2 clock disabled
1: DAC2 clock enabled during sleep and stop modes
Bit 16 DAC1SMEN: DAC1 clock enable
Set and cleared by software.
0: DAC1 clock disabled
1: DAC1 clock enabled during sleep and stop modes
Bit 15 Reserved, must be kept at reset value.
276/2083
Reset value: 0x050F 667F
27 26 25 24
RNG AESM
Res.
EN EN
rw rw
11 10 9
SRAM2 CCMSRAM
Res.
SMEN SMEN
rw rw
23 22 21
Res. Res. Res.
8 7 6 5
GPIOG GPIOF
Res.
SMEN SMEN
rw rw
RM0440 Rev 1
20 19 18
DAC4 DAC3
Res.
SMEN SMEN
rw rw
4 3 2
GPIOE GPIOD GPIOC
SMEN SMEN SMEN
rw rw rw
RM0440
17 16
DAC2 DAC1
SMEN SMEN
rw rw
1 0
GPIOB GPIOA
SMEN SMEN
rw rw