Figure 255. Dma Burst Overview - ST STM32G4 Series Reference Manual

High-resolution timer (HRTIM)
The burst DMA feature is only available for one DMA channel, but any of the 6 channels can
be selected for burst DMA transfers.
The principle is to program which registers are to be written by DMA. The master timer and
TIMA..E have the burst DMA update register, where most of their control and data registers
are associated with a selection bit: HRTIM_BDMUPR, HRTIM_BDTAUPR to
HRTIM_BDTEUPR (this is applicable only for registers with write accesses). A redirection
mechanism allows to forward the DMA write accesses to the HRTIM registers automatically,
as shown on
DMA controller
When the DMA trigger occurs, the HRTIM generates multiple 32-bit DMA requests and
parses the update register. If the control bit is set, the write access is redirected to the
associated register. If the bit is reset, the register update is skipped and the register parsing
is resumed until a new bit set is detected, to trigger a new request. Once the 6 update
registers (HRTIM_BDMUPR, 5x HRTIM_BDTxUPR) are parsed, the burst is completed and
the system is ready for another DMA trigger (see the flowchart on
Note: Any trigger occurring while the burst is on-going is discarded, except if it occurs during the
very last data transfer.
The burst DMA mode is permanently enabled (there is no enable bit). A burst DMA
operation is started by the first write access into the HRTIM_BDMADR register.
It is only necessary to have the DMA controller pointing to the HRTIM_BDMADR register as
the destination, in the memory, to the peripheral configuration with the peripheral increment
mode disabled (the HRTIM handles internally the data re-routing to the final destination
register).
To re-initialize the burst DMA mode if it was interrupted during a transaction, it is necessary
to write at least to one of the 6 update registers.
906/2083
Figure 255.

Figure 255. DMA burst overview

DMA burst controller
DMA requests
RM0440 Rev 1
HRTIM_PERBR
HRTIM_REPBR
HRTIM_CMP1BR
HRTIM_CMP1BCR
HRTIM_CMP2BR
HRTIM_CMP3BR
HRTIM_CMP4BR
Registers parsing
HRTIM_BDTCUPR
DMA burst
update
HRTIM_BDTBUPR
registers
(6 registers)
HRTIM_BDTAUPR
HRTIM_BDMADR
DMA unique
destination
RM0440
Re-direction
demultiplexer
MS32340V1
Figure 256).