Figure 561. Mute Mode Using Idle Line Detection - ST STM32G4 Series Reference Manual

RM0440
The non addressed devices can be placed in Mute mode by means of the muting function.
To use the Mute mode feature, the MME bit must be set in the LPUART_CR1 register.
Note: When FIFO management is enabled and MME is already set, MME bit must not be cleared
and then set again quickly (within two lpuart_ker_ck cycles), otherwise Mute mode might
remain active.
When the Mute mode is enabled:
•
none of the reception status bits can be set;
•
all the receive interrupts are inhibited;
•
the RWU bit in LPUART_ISR register is set to '1'. RWU can be controlled automatically
by hardware or by software, through the MMRQ bit in the LPUART_RQR register,
under certain conditions.
The LPUART can enter or exit from Mute mode using one of two methods, depending on
the WAKE bit in the LPUART_CR1 register:
•
Idle Line detection if the WAKE bit is reset,
•
Address Mark detection if the WAKE bit is set.
Idle line detection (WAKE=0)
The LPUART enters Mute mode when the MMRQ bit is written to 1 and the RWU is
automatically set.
The LPUART wakes up when an Idle frame is detected. The RWU bit is then cleared by
hardware but the IDLE bit is not set in the LPUART_ISR register. An example of Mute mode
behavior using Idle line detection is given in
Note: If the MMRQ is set while the IDLE character has already elapsed, Mute mode will not be
entered (RWU is not set).
If the LPUART is activated while the line is IDLE, the idle state is detected after the duration
of one IDLE frame (not only after the reception of one character frame).
4-bit/7-bit address mark detection (WAKE=1)
In this mode, bytes are recognized as addresses if their MSB is a '1' otherwise they are
considered as data. In an address byte, the address of the targeted receiver is put in the 4
or 7 LSBs. The choice of 7 or 4 bit address detection is done using the ADDM7 bit. This 4-
Low-power universal asynchronous receiver transmitter (LPUART)

Figure 561. Mute mode using Idle line detection

Data 1 Data 2
RX
RWU
MMRQ written to 1
RM0440 Rev 1
Figure 561.
Data 3 Data 4 IDLE
Mute mode
Idle frame detected
RXNE RXNE
Data 5 Data 6
Normal mode
MSv31154V1
1655/2083
1692