Figure 267. Counter Timing Diagram With Prescaler Division Change From 1 To 2 - ST STM32G4 Series Reference Manual

Advanced-control timers (TIM1/TIM8/TIM20)
The time-base unit includes:
•
Counter register (TIMx_CNT)
•
Prescaler register (TIMx_PSC)
•
Auto-reload register (TIMx_ARR)
•
Repetition counter register (TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output tim_cnt_ck, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note: The counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.
Prescaler description
The prescaler divides the counter clock frequency by any factor between 1 and 65536. It is
based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It
can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 267
ratio is changed on the fly.

Figure 267. Counter timing diagram with prescaler division change from 1 to 2

Update event (UEV)
Prescaler control register
Prescaler counter
1048/2083
and Figure 268 give some examples of the counter behavior when the prescaler
tim_psc_ck
CEN
tim_cnt_ck
F7
Counter register
Write a new value in TIMx_PSC
Prescaler buffer
F8 F9 FA FB FC
0
0
0
RM0440 Rev 1
01 02
00
1
1
0 1 0 1 0 1
RM0440
03
0 1
MSv50998V1