Figure 115. Left Alignment (Offset Enabled, Signed Value) - ST STM32G4 Series Reference Manual

RM0440
12-bit data
bit15
SEXT D11
10-bit data
bit15
SEXT D9
8-bit data
bit15
SEXT D7
6-bit data
bit15
SEXT SEXT SEXT SEXT SEXT SEXT SEXT
Gain compensation
When GCOMP bit is set in ADC_CFGR2 register, the gain compensation is activated on all
the converted data. After each conversion, data is calculated with the following formula.
As GCOMPCOEFF can be programmed from 0 to 16383, the actual gain compensation
factor can range from 0 to 3.999756.
Before storing the resulting data in RDATA or JDATAx registers, the LSB−1 value is
evaluated to round up the data and minimize the error.
The gain compensation is also effective for the oversampling. When the gain compensation
is used for the oversampling mode, the gain calculation is performed after the accumulation
and right-shift operations to minimize the power consumption (the gain calculation is done
only once instead of at each conversion).
Offset compensation
When SATEN bit is set in ADC_OFRy register during offset operation, data are unsigned. All
the offset data will saturate at 0x000, and when OFFSETPOS bit is set offset direction is
positive then the data will saturate at 0xFFF. (These are example of 12 bit mode). When 8
bit mode, it saturate at 0x00 and 0xFF respectively.
The analog watchdog comparison is performed on unsigned values, after offset and gain
compensation. For correct watchdog operation, the data after offset compensation must be
in unsigned format (SATEN bit set to 1 in ADC_OFRy register).

Figure 115. Left alignment (offset enabled, signed value)

D10 D9 D8 D7
D8 D7 D6 D5
D6 D5 D4 D3
(
DATA = DATA adc result
RM0440 Rev 1
Analog-to-digital converters (ADC)
bit7
D6 D5 D4 D3
bit7
D4 D3 D2 D1
bit7
D2 D1 D0 0
bit7
SEXT SEXT D5
) × (
GCOMPCOEFF
D2 D1 D0 0
D0 0 0 0
0 0 0 0
D4 D3 D2 D1
) ⁄
4096
bit0
0 0
bit0
0 0
bit0
0 0
bit0
D0 0
MS31018V1
609/3748
683