Figure 77. Ncs When Ckmode = 1 In Ddr Mode (T = Clk Period); Figure 78. Ncs When Ckmode = 1 With An Abort (T = Clk Period) - ST STM32G4 Series Reference Manual

Quad-SPI interface (QUADSPI)
When CKMODE = 1 ("mode3") and DDRM = 1 (DDR mode), nCS falls one CLK cycle
before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation
final active rising CLK edge, as shown in
with a falling edge, CLK is low when nCS rises, and CLK rises back up one half of a CLK
cycle afterwards.
nCS
SCLK
When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation,
the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs
when an operation is stalled, nCS rises just after the abort is requested and then CLK rises
one half of a CLK cycle later, as shown in
nCS
SCLK
Abort
When not in dual-flash mode (DFM = 0), only FLASH 1 is accessed and thus the BK2_nCS
stays high. In dual-flash mode, BK2_nCS behaves exactly the same as BK1_nCS. Thus, if
there is a FLASH 2 and if the application always stays in dual-flash mode, then FLASH 2
may use BK1_nCS and the pin outputting BK2_nCS can be used for other functions.
546/2083

Figure 77. nCS when CKMODE = 1 in DDR mode (T = CLK period)

T

Figure 78. nCS when CKMODE = 1 with an abort (T = CLK period)

T
Figure 77. Because DDR operations must finish
Figure 78.
RM0440 Rev 1
RM0440
T T/2
MS35321V1
Clock stalled T/2
MS35322V1