Figure 673. Clock Division And Timing Elements - ST STM32G4 Series Reference Manual

RM0440
45.4.2 UCPD resets and clocks
A single reset signal nPReset (APB bus reset) is used.
The register section of UCPD is directly clocked on PClk.
The main functional part is clocked on UsbpdClk. It can be pre-scaled to a more appropriate
frequency using PSC_USBPDCLK[2:0].
The receiver is designed to work for any clock input from 6 to 18 MHz. Performance may be
lower in the range 6 to 9 MHz.
The following diagram shows the main elements relating to the clocks and other timing
elements that need to be set to appropriate values.
UsbpdClk
(HSI16)
PClk
Refer to the USB PD specification in order to program the fixed delays. Note that for
tTransitionWindow and especially for tInterFrameGap the clock frequency uncertainty
should be taken into account in order to respect the timings in all cases.
45.4.3 Physical layer protocol
The physical layer covers the signaling underlying the USB Power Delivery specification. Its
main function (transmit side) is to form packets according to the defined packet format
including generally:
–
–
–
–
–
–
A final step of Bi-phase Mark encoding (BMC) is done before transmission on a CC pin.
There are also timing requirements to be met.

Figure 673. Clock division and timing elements

Clock pre-scaler
/PSC_USBPDCLK[2:0]
0: /1
1: /2
2: /4
3: /8
4: /16
Preamble
Start of packet (ordered set)
Payload: header
Payload: data (with encoded data)
Cyclic redundancy check (CRC) information
End of packet
USB Type-C™ / USB Power Delivery interface (UCPD)
Clock division
"Half bit" clock divider
/(HBITCLKDIV[5:0]+1)
/(TRANSWIN[4:0]+1)
RM0440 Rev 1
~ 600 kHz
"tTransitionWindow"
timing generator
"tInterFrameGap"
timing generator
/(IFRGAP[4:0]+1)
BMC Receiver
(9 to 18 MHz
normal range)
BMC Transmitter
Registers
MSv45536V1
2003/2083
2040