Figure 574. Master And Three Independent Slaves - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus
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RM0440
Rx shift register
Tx shift register
1. NSS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to
prevent any MODF error.
2. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their
MISO pin set as alternate function open-drain (see
38.5.4
Multi-master communication
Unless SPI bus is not designed for a multi-master capability primarily, the user can use build
in feature which detects a potential conflict between two nodes trying to master the bus at
the same time. For this detection, NSS pin is used configured at hardware input mode.
The connection of more than two SPI nodes working at this mode is impossible as only one
node can apply its output on a common data line at time.
When nodes are non active, both stay at slave mode by default. Once one node wants to
overtake control on the bus, it switches itself into master mode and applies active level on
the slave select input of the other node via dedicated GPIO pin. After the session is
completed, the active slave select signal is released and the node mastering the bus
temporary returns back to passive slave mode waiting for next session start.

Figure 574. Master and three independent slaves

SPI clock
generator
Master
Serial peripheral interface / inter-IC sound (SPI/I2S)
(1)
NSS
MISO
MOSI
MOSI
SCK
IO1
IO2
IO3
MISO
MOSI
Section 8.3.7: I/O alternate function
RM0440 Rev 1
MISO
Tx shift register
Rx shift register
SCK
NSS
Slave 1
MISO
Tx shift register
MOSI
Rx shift register
SCK
NSS
Slave 2
Tx shift register
Rx shift register
SCK
NSS
Slave 3
input/output.
MSv39626V1
1699/2083
1750

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