Figure 346. Up-Counting Encoder Error Detection - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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Advanced-control timers (TIM1/TIM8/TIM20)

The error assertion is delayed to the transition 0 to 1 when in up-counting. This is cope with

narrow index pulses in gated A and B mode, as shown on

Figure 346. Up-counting encoder error detection

Error detected

Error detected

Abort (index detection)

RM0440 Rev 1

Error asserted

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