Reset And Clock Control (Rcc); Reset; Power Reset; System Reset - ST STM32G4 Series Reference Manual

RM0440
6

Reset and clock control (RCC)

6.1

Reset

There are three types of reset, defined as system reset, power reset and RTC domain reset.
6.1.1

Power reset

A power reset is generated when one of the following events occurs:
1. Power-on reset (POR) or Brown-out reset (BOR).
2. when exiting from Standby mode.
3. when exiting from Shutdown mode.
A Brown-out reset, including power-on or power-down reset (POR/PDR), sets all registers to
their reset values except the RTC domain.
When exiting Standby mode, all registers in the V
Registers outside the V
control) are not impacted.
When exiting Shutdown mode, a Brown-out reset is generated, resetting all registers except
those in the RTC domain.
6.1.2

System reset

A system reset sets all registers to their reset values except the reset flags in the clock
control/status register (RCC_CSR) and the registers in the RTC domain.
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog event (WWDG reset)
3. Independent watchdog event (IWDG reset)
4. A software reset (SW reset) (see
5. Low-power mode security reset (see
6. Option byte loader reset (see
7. A Brown-out reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see
NRST pin (external reset)
Through specific option bits (NRST_MODE), the NRST pin is configurable for operating as:
•
Reset input/output (default at device delivery)
Any valid reset signal on the pin is propagated to device internal logic and all internal
reset sources are externally driven through a pulse generator to this pin. The GPIO
functionality (PG10) is not available. The pulse generator guarantees a minimum reset
pulse duration of 20 µs for each internal reset source to be output on the NRST pin. An
internal reset holder option can be used, if enabled in the option bytes, to ensure that
the pin is pulled low until its voltage meets VIL threshold. This function guarantee the
detection of internal reset sources by external components when the line faces a
domain (RTC, WKUP, IWDG, and Standby/Shutdown modes
CORE
Option byte loader
Section 6.4.28: Control/status register
RM0440 Rev 1
Reset and clock control (RCC)
domain are set to their reset value.
CORE
Software reset)
Low-power mode security
reset)
(RCC_CSR)).
reset)
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