ST STM32G4 Series Reference Manual page 26

Contents
27.3.26 Direction bit output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
27.3.27 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
27.3.28 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
27.3.29 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
27.3.30 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
27.3.31 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
27.3.32 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
27.3.33 TIM1/TIM8/TIM20 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
27.3.34 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
27.4 TIM1/TIM8/TIM20 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . .1130
27.5 TIM1/TIM8/TIM20 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1130
27.6 TIM1/TIM8/TIM20 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1131
27.6.1
27.6.2
27.6.3
27.6.4
27.6.5
27.6.6
27.6.7
27.6.8
27.6.9
27.6.10 TIMx capture/compare mode register 2 [alternate]
27.6.11 TIMx capture/compare enable register
27.6.12 TIMx counter (TIMx_CNT)(x = 1, 8, 20) . . . . . . . . . . . . . . . . . . . . . . . 1157
27.6.13 TIMx prescaler (TIMx_PSC)(x = 1, 8, 20) . . . . . . . . . . . . . . . . . . . . . 1157
27.6.14 TIMx auto-reload register (TIMx_ARR)(x = 1, 8, 20) . . . . . . . . . . . . . 1158
27.6.15 TIMx repetition counter register (TIMx_RCR)(x = 1, 8, 20) . . . . . . . . 1158
27.6.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8, 20) . . . . . . 1159
27.6.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8, 20) . . . . . . 1159
27.6.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8, 20) . . . . . . 1160
27.6.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8, 20) . . . . . . 1161
27.6.20 TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8, 20) . . . . 1162
27.6.21 TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8, 20) . . . . . . 1166
26/2083
TIMx control register 1 (TIMx_CR1)(x = 1, 8, 20) . . . . . . . . . . . . . . . 1131
TIMx control register 2 (TIMx_CR2)(x = 1, 8, 20) . . . . . . . . . . . . . . . 1132
TIMx slave mode control register (TIMx_SMCR)(x = 1, 8, 20) . . . . . 1135
TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8, 20) . . . . . 1139
TIMx status register (TIMx_SR)(x = 1, 8, 20) . . . . . . . . . . . . . . . . . . . 1140
TIMx event generation register (TIMx_EGR)(x = 1, 8, 20) . . . . . . . . . 1143
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8, 20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8, 20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8, 20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
(TIMx_CCMR2)(x = 1, 8, 20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150
(TIMx_CCER)(x = 1, 8, 20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153
RM0440 Rev 1
RM0440