ST STM32G4 Series Reference Manual page 144

Embedded Flash memory (FLASH) for category 3 devices
Table 17. Flash interface - register map and reset values (continued)
Offset Register
FLASH_
WRP1BR
0x30
Reset value
FLASH_
PCROP2SR
0x44
Reset value
FLASH_
PCROP2ER
0x48
Reset value
FLASH_
WRP2AR
0x4C
Reset value
FLASH_
WRP2BR
0x50
Reset value
FLASH_
SEC1R
0x70
Reset value
FLASH_
SEC2R
0x74
Reset value
Refer to
144/2083
X X X X X X X X
Section 2.2 on page 78
WRP1B_END[6:0]
X X X X X X X
X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X
WRP2A_END[6:0]
X X X X X X X
WRP2B_END[7:0]
X
for the register boundary addresses.
RM0440 Rev 1
RM0440
WRP1B_STRT[6:0]
X X X X X X X
PCROP2_STRT[14:0]
PCROP2_END[14:0]
WRP2A_STRT[6:0]
X X X X X X X
WRP2B_STRT[7:0]
X X X X X X X X
SEC_SIZE1[7:0]
X X X X X X X X
SEC_SIZE2[7:0]
X X X X X X X X