Figure 278. Counter Timing Diagram, Internal Clock Divided By N; Figure 279. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used - ST STM32G4 Series Reference Manual

Advanced-control timers (TIM1/TIM8/TIM20)
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag

Figure 279. Counter timing diagram, update event when repetition counter is not used

Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
1056/2083

Figure 278. Counter timing diagram, internal clock divided by N

tim_psc_ck
tim_cnt_ck
20
(UIF)
tim_pasc_ck
CEN
tim_cnt_ck
05
(UIF)
FF
register
Write a new value in TIMx_ARR
1F
04 03 02 01 00
RM0440 Rev 1
00 36
36 35 34 33 32
36
RM0440
MSv62308V1
31 30 2F
MSv62309V1