ST STM32G4 Series Reference Manual page 784

Operational amplifiers (OPAMP)
24.5.12 OPAMP6 timer controlled mode register (OPAMPx_TCMR) (x = 1...6)
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29
LOCK
rw
15 14 13
Bit 31 LOCK: OPAMP6_TCMR lock
This bit is write-once. It is set by software. It can only be cleared by a system reset.
This bit is used to configure the OPAMP6_TCMR register as read-only.
0: OPAMP6_TCMR is read-write
1: OPAMP6_TCMR is read-only
Bits 30:6 Reserved, must be kept at reset value.
Bit 5 T20CM_EN: TIM20 controlled mux mode enable
This bit is set and cleared by software. It is used to control automatically the switch between the
default selection (VP_SEL and VM_SEL) and the secondary selection (VPS_SEL and
VMS_SEL) of the inverting and non inverting inputs. This automatic switch is triggered by the
TIM20 CC6 output arriving on the OPAMP6 input multiplexers.
0: Automatic switch is disabled.
1: Automatic switch is enabled.
Bit 4 T8CM_EN: TIM8 controlled mux mode enable
This bit is set and cleared by software. It is used to control automatically the switch between the
default selection (VP_SEL and VM_SEL) and the secondary selection (VPS_SEL and
VMS_SEL) of the inverting and non inverting inputs. This automatic switch is triggered by the
TIM8 CC6 output arriving on the OPAMP6 input multiplexers.
0: Automatic switch is disabled.
1: Automatic switch is enabled.
784/2083
28 27 26 25
12 11 10 9
Res.
24 23 22 21
Res.
8 7 6 5
T20CM
_EN
rw
RM0440 Rev 1
20 19 18
4 3 2
T8CM_ T1CM_
VPS_SEL
EN EN
rw rw rw
RM0440
17 16
1 0
VMS_
SEL
rw rw