System And Memory Overview; System Architecture - ST STM32G4 Series Reference Manual

RM0440
2

System and memory overview

2.1

System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
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Up to five masters:
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Up to nine slaves:
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The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in
®
Cortex -M4 with FPU core I-bus
®
Cortex -M4 with FPU core D-bus
®
Cortex -M4 with FPU core S-bus
DMA1
DMA2
Internal Flash memory on te ICode bus
Internal Flash memory on DCode bus
Internal SRAM1
Internal SRAM2
Internal CCM SRAM
AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
AHB2 peripherals
Flexible Memory Controller (FMC)
QUAD SPI memory interface (QUADSPI)
Figure 1:
RM0440 Rev 1
System and memory overview
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