Figure 586. I2S Block Diagram - ST STM32G4 Series Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
38.7 I2S functional description
38.7.1 I2S general description
The block diagram of the I2S is shown in
MOSI/SD
MISO
NSS/WS
CK
I2SMOD
MCK
1. MCK is mapped on the MISO pin.
The SPI can function as an audio I2S interface when the I2S capability is enabled (by
setting the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same
pins, flags and interrupts as the SPI.
1720/2083

Figure 586. I2S block diagram

Master control logic
SPI
baud rate generator
I2S_ CK
Figure 586.
Address and data bus
Tx buffer
BSY OVR MODF
16-bit
Shift register
16-bit
Rx buffer
I2SCFG
I2SSTD
[1:0]
[1:0]
Bidi CRC
Bidi
mode OE
LSB
SPE BR2 BR1 BR0 MSTR CPOL CPHA
First
2
I S clock generator
MCKOE ODD I2SDIV[7:0]
RM0440 Rev 1
CRC CH
UDR TxE RxNE
ERR SIDE
LSB first
Communication
CH
CK
DATLEN
LEN
[1:0]
POL
I2S
I2SE
MOD
CRC Rx
SSI
Next DFF only SSM
EN
I2SxCLK
RM0440
FRE
control
MS32126V1