Adc Clock; Rtc Clock - ST STM32G4 Series Reference Manual

Reset and clock control (RCC)
LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY
set by hardware), and after the RTC clock has been selected by RTCSEL.
The CSS on LSE is working in all modes except VBAT. It is working also under system reset
(excluding power on reset). If a failure is detected on the external 32 kHz oscillator, the LSE
clock is no longer supplied to the RTC but no hardware action is made to the registers. If the
HSI16 was in PLL-mode, this mode is disabled.
In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
the software (see
(RCC_CIFR),
The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
(disabling LSEON), and change the RTC clock source (no clock or LSI or HSE, with
RTCSEL), or take any required action to secure the application.
The frequency of LSE oscillator have to be higher than 30 kHz to avoid false positive CSS
detection.
6.2.11

ADC clock

The ADC clock is derived from the system clock, or from the PLL "P" output. It can reach
170 MHz and can be divided by the following prescalers values:
1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADCx_CCR register. It is
asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB
clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This
programmable factor is configured using the CKMODE bit fields in the ADCx_CCR.
If the programmed factor is '1', the AHB prescaler must be set to '1'.
6.2.12

RTC clock

The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the
selection cannot be modified without resetting the RTC domain. The system must always be
configured so as to get a PCLK frequency greater then or equal to the RTCCLK frequency
for a proper operation of the RTC.
The LSE clock is in the RTC domain, whereas the HSE and LSI clocks are not.
Consequently:
•
If LSE is selected as RTC clock:
–
• If LSI is selected as the RTC clock:
–
•
If the HSE clock divided by a prescaler is used as the RTC clock:
–
When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system
reset.
240/2083
Clock interrupt enable register
Clock interrupt clear register
The RTC continues to work even if the V
V supply is maintained.
BAT
The RTC state is not guaranteed if the V
The RTC state is not guaranteed if the V
voltage regulator is powered off (removing power from the V
(RCC_CIER),
(RCC_CICR)).
RTC domain control register
supply is switched off, provided the
DD
supply is powered off.
DD
supply is powered off or if the internal
DD
RM0440 Rev 1
RM0440
Clock interrupt flag register
(RCC_BDCR). This
domain).
CORE