ST STM32G4 Series Reference Manual page 135

RM0440
Bits 29:28 NRST_MODE[1:0]
Embedded Flash memory (FLASH) for category 3 devices
Bit 31 Reserved, must be kept at reset value.
Bit 30 IRHEN: Internal reset holder enable bit
0: Internal resets are propagated as simple pulse on NRST pin
1: Internal resets drives NRST pin low until it is seen as low level
00: Reserved
01: Reset Input only: a low level on the NRST pin generates system reset,
internal RESET not propagated to the NSRT pin
10: GPIO: standard GPIO pad functionality, only internal RESET possible
11: Bidirectional reset: NRST pin configured in reset input/output mode (legacy
mode)
Bit 27 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 26 nSWBOOT0: Software BOOT0
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PB8/BOOT0 pin
Bit 25 CCMSRAM_RST: CCM SRAM Erase when system reset
0: CCM SRAM erased when a system reset occurs
1: CCM SRAM is not erased when a system reset occurs
Bit 24 SRAM_PE: SRAM1 and CCM SRAM parity check enable
0: SRAM1 and CCM SRAM parity check enable
1: SRAM1 and CCM SRAM parity check disable
Bit 23 nBOOT1: Boot configuration
Together with the BOOT0 pin, this bit selects boot mode from the Flash main
memory, SRAM1 or the System memory. Refer to
configuration.
Bit 22 DBANK:
0: Single bank mode with 128 bits data read width
1: Dual bank mode with 64 bits data
This bit can only be written when PCROPA/B is disabled.
Bit 21 Reserved, must be kept cleared
Bit 20 BFB2: Dual-bank boot
0: Dual-bank boot disable
1: Dual-bank boot enable
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
RM0440 Rev 1
Section 2.6: Boot
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