Table 210. Interleaved Mode Selection - ST STM32G4 Series Reference Manual

High-resolution timer (HRTIM)
This mode is enabled by writing HALF bit to 1 in the HRTIM_TIMxCR register. When the
HRTIM_PERxR register is written, it causes an automatic update of the compare 1 value
with HRTIM_PERxR/2 value.
The output on which a square wave is generated must be programmed to have one
transition on CMP1 event, and one transition on the period event, as follows:
–
–
The HALF mode overrides the content of the HRTIM_CMP1xR register. The access to the
HRTIM_PERxR register only causes compare 1 internal register to be updated. The user-
accessible HRTIM_CMP1xR register is not updated with the HRTIM_PERxR / 2 value.
When the preload is enabled (PREEN = 1, MUDIS, TxUDIS), compare 1 active register is
refreshed on the update event. If the preload is disabled (PREEN= 0), compare 1 active
register is updated as soon as HRTIM_PERxR is written.
The period must be greater than or equal to 6 periods of the f
CKPSC[2:0] = 0, 0x60 if CKPSC[2:0] = 1, 0x30 if CKPSC[2:0] = 2,...) when the HALF mode
is enabled.
Interleaved mode
This mode complements the Half mode and helps the implementation of interleaved
topologies.
It allows to re-compute automatically the content of compare registers when the
HRTIM_PERxR value is updated.
The selection is done using the HALF bit and the IL[1:0] bits in HRTIM_MCR and
HRTIM_TIMxCR registers, as shown on the
HALF bit
0
0
0
0
1
Table 211
registers is overridden. The corresponding compare events can be used to trigger an output
set / reset or to reset a slave timer.
820/2083
HRTIM_SETxyR = 0x0000 0008, HRTIM_RSTxyR = 0x0000 0004, or
HRTIM_SETxyR = 0x0000 0004, HRTIM_RSTxyR = 0x0000 0008

Table 210. Interleaved mode selection

INTLVD
[1:0] bits
00
01
10
11
xx
gives the compare values for the 3 available modes. The content of the compare
Table 210
Triple interleaved (120°)
Quad interleaved (90°)
Dual interleaved (180°)
RM0440 Rev 1
clock (0xC0 if
HRTIM
below.
Mode
Disabled
Reserved
RM0440