ST STM32G4 Series Reference Manual page 413

Advanced arm-based 32-bit mcus

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Pending register 1 (EXTI_PR1)

Address offset: 0x14

Reset value: undefined

Bits 31:29 PIFx: Pending interrupt flag on line x (x = 31 to 29)

Bits 28:23 Reserved, must be kept at reset value.

Bits 22:19 PIFx: Pending interrupt flag on line x (x = 22 to 19)

Bits 17:0 PIFx: Pending interrupt flag on line x (x = 17 to 0)

Interrupt mask register 2 (EXTI_IMR2)

Address offset: 0x20

Reset value: 0x0000 0187

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the interrupt line. This bit

is cleared by writing a '1' to the bit.

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the interrupt line. This bit

is cleared by writing a '1' to the bit.

Bit 18 Reserved, must be kept at reset value.

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the interrupt line. This bit

is cleared by writing a '1' to the bit.

Extended interrupts and events controller (EXTI)

RM0440 Rev 1

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