Figure 628. I2C Block Diagram - ST STM32G4 Series Reference Manual

Inter-integrated circuit (I2C) interface
If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also
available.
40.4.1 I2C block diagram
The block diagram of the I2C interface is shown in
I2c_ker_ck
I2c_pclk
The I2C is clocked by an independent clock source which allows to the I2C to operate
independently from the PCLK frequency.
For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to
1818/2083

Figure 628. I2C block diagram

I2CCLK
Wakeup
on
address
match
PCLK
Section 40.3: I2C implementation.
Figure
Data control
Digital
Shift register
noise
filter
SMBUS
PEC
generation/
check
Clock control
Master clock
Digital
generation
noise
Slave clock
filter
stretching
SMBus
Timeout
check
SMBus Alert
control &
status
Registers
APB bus
RM0440 Rev 1
628.
Analog
noise
GPIO
filter
logic
Analog
noise
GPIO
filter
logic
RM0440
I2C_SDA
I2C_SCL
I2C_SMBA
MSv46198V2