Table 299. Effect Of Low-Power Modes On Tim6/Tim7 - ST STM32G4 Series Reference Manual

Basic timers (TIM6/TIM7)
30.3.8 Debug mode
When the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the TIMx
counter can either continue to work normally or be stopped.
The behavior in debug mode can be programmed with a dedicated configuration bit per
timer in the Debug support (DBG) module.
For more details, refer to section Debug support (DBG).
30.3.9 TIM6/TIM7 low-power modes
Mode
Sleep
Stop
Standby
30.3.10 TIM6/TIM7 interrupts
The TIM6/TIM7 can generate a single interrupt, as shown in
Interrupt
acronym
TIM6
TIM7
30.4 TIM6/TIM7 registers
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
30.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7)
Address offset: 0x00
Reset value: 0x0000
15 14 13
DITH
Res. Res. Res.
1412/2083

Table 299. Effect of low-power modes on TIM6/TIM7

No effect, peripheral is active. The interrupts can cause the device to exit from Sleep
The timer operation is stopped and the register content is kept. No interrupt can be
The timer is powered-down and must be reinitialized after exiting the Standby mode.
Interrupt event Event flag
Update
Section 1.2 on page 71
12 11 10 9
UIFRE
Res. Res.
EN MAP
rw rw
Description
mode.
generated.
Table 300. Interrupt request
Enable
control bit
UIF UIE
for a list of abbreviations used in register descriptions.
8 7 6
Res. ARPE Res.
rw
RM0440 Rev 1
Table 300.
Exit from
Interrupt
Sleep
clear method
mode
write 0 in UIF Yes
5 4 3 2
Res. Res. OPM URS
rw rw
RM0440
Exit from
Stop and
Standby
mode
No
1 0
UDIS CEN
rw rw