Table 44. Crs Register Map And Reset Values - ST STM32G4 Series Reference Manual

Clock recovery system (CRS)
7.6.5 CRS register map
Offset Register
CRS_CR
0x00
Reset value
CRS_CFGR
0x04
Reset value 0
CRS_ISR
0x08
Reset value 0
CRS_ICR
0x0C
Reset value
Refer to
306/2083

Table 44. CRS register map and reset values

SYNC SYNC
SRC DIV
[1:0] [2:0]
1 0 0 0 0 0
FECAP[15:0]
0 0 0 0 0 0 0 0
Section 2.2 on page 78
FELIM[7:0]
0 1 0 0 0 1 0 1
0 0 0 0 0 0 0 0
for the register boundary addresses.
RM0440 Rev 1
TRIM[6:0]
1 0 0 0 0 0 0 0
RELOAD[15:0]
0 1 1 1 0 1 1 0
0 0 0
RM0440
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0
0 0 0 0