ST STM32G4 Series Reference Manual page 935

RM0440
Bit 7 CPT1C: Capture 1 interrupt flag clear
Writing 1 to this bit clears the CPT1 flag in HRTIM_TIMxISR register
Bit 6 UPDC: Update interrupt flag clear
Writing 1 to this bit clears the UPD flag in HRTIM_TIMxISR register
Bit 5 Reserved, must be kept at reset value.
Bit 4 REPC: Repetition interrupt flag clear
Writing 1 to this bit clears the REP flag in HRTIM_TIMxISR register
Bit 3 CMP4C: Compare 4 interrupt flag clear
Writing 1 to this bit clears the CMP4 flag in HRTIM_TIMxISR register
Bit 2 CMP3C: Compare 3 interrupt flag clear
Writing 1 to this bit clears the CMP3 flag in HRTIM_TIMxISR register
Bit 1 CMP2C: Compare 2 interrupt flag clear
Writing 1 to this bit clears the CMP2 flag in HRTIM_TIMxISR register
Bit 0 CMP1C: Compare 1 interrupt flag clear
Writing 1 to this bit clears the CMP1 flag in HRTIM_TIMxISR register
26.5.15 HRTIM timer x DMA interrupt enable register (HRTIM_TIMxDIER)
(x = A to F)
Address offset: Block A: 0x08C
Address offset: Block B: 0x10C
Address offset: Block C: 0x18C
Address offset: Block D: 0x20C
Address offset: Block E: 0x28C
Address offset: Block F: 0x30C
Reset value: 0x0000 0000
31 30 29
DLYPR RSTx2
Res. RSTDE
TDE
rw rw
15 14 13
DLYPR RSTx2I
Res. RSTIE
TIE
rw rw
28 27 26 25
SETx2 RSTx1 SETx1
DE DE DE DE
rw rw rw rw
12 11 10 9
SETx2I RSTx1I SET1xI
E E E E
rw rw rw rw
24 23 22
CPT2D CPT1D
UPDDE
E E
rw rw rw
8 7 6
CPT2IE CPT1IE UPDIE
rw rw rw
RM0440 Rev 1
High-resolution timer (HRTIM)
21 20 19 18
CMP4D CMP3D
Res. REPDE
E E
rw rw rw
5 4 3 2
CMP4I CMP3I
Res. REPIE
E E
rw rw rw
17 16
CMP2D CMP1D
E E
rw rw
1 0
CMP2I CMP1I
E E
rw rw
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