Table 279. Tim Input/Output Pins; Figure 436. Tim16/Tim17 Block Diagram - ST STM32G4 Series Reference Manual

RM0440
tim_ker_ck
tim_pclk
IRQ interface
tim_it
tim_cc1_dma
tim_upd_dma
DMA interface
tim_com_dma
tim_ti1_in0
TIMx_CH1
tim_ti1_in[1..15]
tim_ocref_clr[7..0]
tim_sys_brk
TIM_BKIN
tim_brk_cmp[7:1]
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
1. Refer to Section 29.4.15: Using the break function
29.4.2 TIM15/TIM16/TIM17 pins and internal signals
Table 279
Pin name
TIM_CH1
TIM_CH2
TIM_CH1N
TIM_BKIN
1. Available for TIM15 only.

Figure 436. TIM16/TIM17 block diagram

tim_psc_ck
PSC
prescaler
Input
tim_ti1fp1
filter &
Prescaler
edge
tim_ic1
detector
SBIF
(1)
Break circuitry
and Table 280 in this section summarize the TIM inputs and outputs.

Table 279. TIM input/output pins

Signal type
Input/Output
(1)
Output
Input / Output
General-purpose timers (TIM15/TIM16/TIM17)
Counter Enable (CEN)
Auto-reload register
UEV
Stop, clear or up/down
tim_cnt_ck
+/-
CNT counter
C1I
U
Capture/compare 1 register
tim_ocref_clr_int
BIF
tim_brk
for details.
Timer multi-purpose channels.
Each channel be used for capture, compare, or PWM.
TIM_CH1 and TIM_CH2 can also be used as external clock
(below 1/4 of the tim_ker_ck clock) and external trigger inputs.
Timer complementary outputs, derived from TIM_CHx outputs
with the possibility to have deadtime insertion.
Break input. This input can also be configured in bidirectional
mode.
RM0440 Rev 1
REP
register
Repetition
counter
DTG registers
CC1I
tim_oc1ref
Output
DTG
Control
Description
UI
UEV
tim_oc
TIMx_CH1
TIMx_CH1N
tim_oc1n
MSv62372V1
1301/2083
1399