ST STM32G4 Series Reference Manual page 658

Analog-to-digital converters (ADC)
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN=1.
0: DMA One Shot mode selected
1: DMA Circular mode selected
For more details, refer to
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the
ADCx_CCR register.
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows to use
the DMA to manage automatically the converted data. For more details, refer to
conversions using the
0: DMA disabled
1: DMA enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the
ADCx_CCR register.
20.6.5 ADC configuration register 2 (ADC_CFGR2)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
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Section : Managing conversions using the DMA
DMA.
28 27 26 25
SMPTRI SWTRI
BULB
G G
rw rw rw
12 11 10 9
ROV
Res. TROVS
SM
rw rw
24 23 22
Res. Res. Res.
8 7 6
OVSS[3:0]
rw rw rw
RM0440 Rev 1
Section : Managing
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OVSR[2:0]
rw rw rw rw
RM0440
17 16
GCOM
Res.
P
rw
1 0
JOVSE ROVSE
rw rw