Flash Bank 2 Wrp Area B Address Register (Flash_Wrp2Br); Flash Securable Area Bank1 Register (Flash_Sec1R) - ST STM32G4 Series Reference Manual

RM0440
3.7.16

Flash Bank 2 WRP area B address register (FLASH_WRP2BR)

Address offset: 0x50
Reset value: 0x00XX 00XX
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:23 Reserved, must be kept cleared
Bits 22:16 WRP2B_END: WRP second area "B" end offset
3.7.17

Flash Securable area bank1 register (FLASH_SEC1R)

Address offset: 0x70
Reset value: 0xFFFX FFXX
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Embedded Flash memory (FLASH) for category 3 devices
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
DBANK=1
WRP2B_END contains the last page of the WRP second area for bank2.
DBANK=0
WRP2B_END contains the last page of the WRP fourth area for all memory.
Bits 15:7 Reserved, must be kept cleared
Bits 6:0 WRP2B_STRT: WRP second area "B" start offset
DBANK=1
WRP2B_STRT contains the first page of the WRP second area for bank2.
DBANK=0
WRP2B_STRT contains the first page of the WRP second area for all memory.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
24 23 22
Res. Res. Res.
8 7 6
Res.
rw rw
RM0440 Rev 1
21 20 19 18
WRP2B_END[7:0]
rw rw rw rw
5 4 3 2
WRP2B_STRT[7:0]
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
SEC_SIZE1
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
BOOT_
Res.
LOCK
rw
1 0
rw rw
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