ST STM32G4 Series Reference Manual page 182

Embedded Flash memory (FLASH) for category 2 devices
Bits 22:16 WRP1A_END: WRP first area "A" end offset
4.7.12 Flash WRP area B address register (FLASH_WRP1BR)
Address offset: 0x30
Reset value: 0x00XX 00XX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:23 Reserved, must be kept cleared
Bits 22:16 WRP1B_END: WRP second area "B" end offset
4.7.13 Flash Securable area register (FLASH_SEC1R)
Address offset: 0x70
Reset value: 0xFFFX FFXX
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
182/2083
WRP1A_END contains the last page of WRP first area.
Bits 15:7 Reserved, must be kept cleared
Bits 6:0 WRP1A_STRT: WRP first area "A" start offset
WRP1A_STRT contains the first page of WRP first area.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
WRP1B_END contains the last page of the WRP second area.
Bits 15:7 Reserved, must be kept cleared
Bits 6:0 WRP1B_STRT: WRP second area "B" start offset
WRP1B_STRT contains the last page of the WRP second area.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
24 23 22
Res. Res. Res.
8 7 6
Res.
rw rw
RM0440 Rev 1
21 20 19 18
WRP1B_END[6:0]
rw rw rw rw
5 4 3 2
WRP1B_STRT[6:0]
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
SEC_SIZE1
rw rw rw rw
RM0440
17 16
rw rw
1 0
rw rw
17 16
BOOT_
Res.
LOCK
rw
1 0
rw rw