ST STM32G4 Series Reference Manual page 62

List of figures
Figure 245. Auxiliary and main outputs during burst mode (DIDLx = 0) . . . . . . . . . . . . . . . . . . . . . . . 890
Figure 246. Deadtime distortion on auxiliary output when exiting burst mode. . . . . . . . . . . . . . . . . . . 890
Figure 247. Counter behavior in synchronized start mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Figure 248. ADC trigger selection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
Figure 249. ADC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
Figure 250. ADC trigger post-scaling in up-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
Figure 251. ADC trigger post-scaling in up/down counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
Figure 252. Combining several updates on a single hrtim_dac_trgx output . . . . . . . . . . . . . . . . . . . . 898
Figure 253. DAC triggers for slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Figure 254. DAC triggers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
Figure 255. DMA burst overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Figure 256. Burst DMA operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
Figure 257. Registers update following DMA burst transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
Figure 258. Buck converter topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
Figure 259. Dual Buck converter management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
Figure 260. Synchronous rectification depending on output current . . . . . . . . . . . . . . . . . . . . . . . . . . 911
Figure 261. Buck with synchronous rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
Figure 262. 3-phase interleaved buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
Figure 263. 3-phase interleaved buck converter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
Figure 264. Transition mode PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
Figure 265. Transition mode PFC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Figure 266. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
Figure 267. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1048
Figure 268. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1049
Figure 269. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
Figure 270. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Figure 271. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Figure 272. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Figure 273. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Figure 274. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Figure 275. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
Figure 276. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
Figure 277. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
Figure 278. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
Figure 279. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . 1056
Figure 280. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . 1058
Figure 281. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Figure 282. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1059
Figure 283. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Figure 284. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . 1060
Figure 285. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1061
Figure 286. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1062
Figure 287. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
Figure 288. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1064
Figure 289. tim_ti2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Figure 290. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Figure 291. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
Figure 292. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Figure 293. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1067
Figure 294. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
62/2083 RM0440 Rev 1
RM0440